Conventionally, Japanese Patent No. 3489358 teaches a SiC (i.e., silicon carbide) semiconductor device having a vertical MOSFET as a vertical insulated gate type transistor. As shown in FIG. 9A, in the device, a longitudinal direction of a P+ conductive type contact region J2 coupled with a P conductive type base region and a longitudinal direction of a N+ conductive type source region J1 and a P conductive type base region are in parallel to a longitudinal direction of a trench J3, which provides a trench gate structure. A contact hole J4 formed in an interlayer insulation film is in parallel to the longitudinal direction of the trench J3. The N+ conductive type source region J1 and the P+ conductive type contact region J2 are electrically coupled with the source electrode through the contact hole.
However, in a conventional semiconductor device, when a cell pitch is reduced for micro-fabrication, a width between the source region J1 coupled with a source electrode and the contact region J2 is narrowed, as shown in FIG. 9B. Thus, contact between the contact region and the source electrode may not be sufficient.